Evaluation of SRAM based FPGA performance by simulating SEU through fault injection

This paper presents the technique and results of Single Event Upsets fault injection in the configuration bit-stream of SRAM-based FPGAs through partial reconfiguration of configuration frames. The Xilinx Virtex5 LX50 is used in the experiments. The Single Event Upset controller macro is used injecting faults to random locations of the FPGA bit-stream. The effects were studied on a design consisting of 4 embedded processor systems implemented in the FPGA. MATLAB is used for developing the external fault injection control environment.