Analysis and design of high performance frequency-interleaved ADC

This paper proposes a frequency-interleaved ADC (FI-ADC) architecture, which can avoid time skew problem existing in time-interleaved ADC (TI-ADC). The analysis filter bank of the FI-ADC is implemented by low order analog filters and can be integrated easily. In addition, prototype of an 8-channel 2GS/s 12-bit FI-ADC is designed. Based on the spurious-free dynamic range (SFDR), the comparison of variation of analog filter coefficients in FI-ADC and time skew in TI-ADC is done. Simulation results show that FI-ADC is more suitable for GHz implementation, and the proposed FI-ADC has a better gain mismatch tolerance than TI-ADC.