Improving and optimizing reliability in future technologies with high-κ dielectrics

Three mechanisms primarily limit gate oxide scaling: bias temperature instability in both NFETs (PBTI) and PFETs (NBTI), and gate dielectric breakdown in NFETs (nTDDB). Strategies for reducing each mechanism are identified, and the overall effect of each mechanism on future scaling is discussed. Specialized ring oscillator structures that aid in the understanding of the effect of both PBTI and NBTI on circuit operation are explored.