Generating test patterns for fault detection in combinational circuits using genetic algorithm

In this paper we propose a method for the automatic test pattern generation for detecting stuck-at-faults in combinational VLSI circuits using genetic algorithm (GA). Derivation of minimal test sets helps to reduce the post-production cost of testing combinational circuits. The GA proves to be an effective algorithm in finding optimum number of test patterns from the highly complex problem space. In this paper results are obtained for single stuck-at-fault in the ISCAS 1989(C17) benchmark circuit.