Extending pre-silicon delay models for post-silicon tasks: Validation, diagnosis, delay testing, and speed binning

All post-silicon tasks - validation, diagnosis, delay testing, and speed-binning - must be carried out by applying vectors to actual chips, and capturing and analyzing responses. Yet, vectors used must be generated and analyzed using pre-silicon models of the circuit. Three comprehensive industrial studies demonstrate that existing approaches for generating such vectors are inadequate, and one major weakness is that existing delay models either do not capture process variations or do not capture advanced delay phenomenon that significantly affect delays. Hence, existing models underestimate the worst case delay leading to selection of non-critical paths and generation of vectors that do not invoke worst case delays. In this paper, we propose a simple notion of bounding approximation and show how it can extend any existing delay model to also capture process variations and to eliminate any underestimation. The main question we investigate is how best to use this approach to select paths and generate or evaluate vectors for post silicon tasks. In particular, we study whether it is better to use this approach to bound simple pin-to-pin delay models or more advanced delay models. At the level of timing analysis, bounded versions of pin-to-pin delay models have lower run-time complexity but looser bounds. However, we conduct path selection for delay testing and vector generation for delay validation and show that bounded versions of more advanced delay models are significantly more efficient in terms of validation cost and runtime complexity.