Effect of threshold voltage implants on single-event error rates of D flip-flops in 28-nm bulk CMOS

To understand the effects of threshold voltage implants on soft-error rate of a D flip-flop, three different designs were created using low, standard, and high voltage threshold implants in a 28-nm bulk technology. Experimental results show that the error rate is nearly the same for the three D flip-flop designs. This work attributes small critical charge and process variations across the flip-flop arrays as the main cause for similar soft-error rate of the flip-flops regardless of the threshold voltage implant.