A low-power circuit technique for domino CMOS logic

Dynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge sharing problems. Domino logic uses one static CMOS inverter at the output of dynamic node which is more noise immune and has less capacitance at the output node. In this paper we have proposed a novel circuit for domino logic which less noise at the output node and has very less power-delay product (PDP) as compared to previous reported articles. The proposed circuit is being compared with previous reported domino logic and the basic domino logic structures in different ways and found to be having least PDP from others.