Design of an ultra-low power 32-bit adder operating at subthreshold voltages in 45-nm FinFET

This paper describes the design of an ultimately low power subthreshold 32-bit adder, implemented in 45-nm technology. Low power design is achieved by using FinFET devices which are nowadays a basic component of very scaled and low power circuits. The circuit was tested in all corners and its consumption is as low as 10fJ per computation with 0.4V supply voltage and maximum operating frequency about 260KHz. A very alluring feature of this design is that it could be speed up to 256MHz in 1.13V supply voltage and consuming only 59.05fJ energy per calculation. Another appealing feature of propose design is its stable and reliable operation with 130mV supply voltage by 3.74 KHz operation frequency. In this mode the design consumes only 43.77fW. This multi-mode design could be used in integrated circuit design which uses power management technique to reduce energy consumption by OS software job assignment. The simulations were done by HSPISE 2008.all model are extracted from FinFET 45nm PTM library.