VLIW - SIMD processor based scalable architecure for parallel classifier node computing

This paper presents a VLIW-SIMD processor based scalable architecture with Data Flow Control (DC) Engine and Classifier Evaluation (CE) Engine for parallel classifier node computation to accelerate the object detection algorithm for embedded applications. The popular algorithm is developed by Viola and Jones [1] with Haar - like features. The architecture has 4-slot very long instruction word (VLIW) processor core and internal memories to hold the integral image data and classifier data. Each VLIW instruction packet has two load/store instruction slots and two 4-way SIMD instruction slots. Generic SIMD instructions are added to the instruction set to compute various classifier parameters in parallel. Nodes in two levels of classifier tree are computed in parallel with the proposed instructions. Fixed point arithmetic is to get faster clock rates at less area. The performance of the architecture is tested using the training data from OpenCV to detect the frontal faces from a set of images. Single instance of the proposed architecture is able detect the faces from CIF resolution images at a rate of 8.33 fps running at 500MHz clock frequency which is 1.6X performance gain over the OpenCV software version running on Pentimum-4, 2GHz processor. Two instances of classifier evaluation engine gives performance of 15.47 fps. The proposed engine is designed using Verilog HDL and it is synthesized using Synopsis Design Compiler with 28nm TSMC target libraries. The clock period is set to 2ns and the timing constraints are met.