Accelerating Hydrocodes with OpenACC, OpenCL and CUDA

Hardware accelerators such as GPGPUs are becoming increasingly common in HPC platforms and their use is widely recognised as being one of the most promising approaches for reaching exascale levels of performance. Large HPC centres, such as AWE, have made huge investments in maintaining their existing scientific software codebases, the vast majority of which were not designed to effectively utilise accelerator devices. Consequently, HPC centres will have to decide how to develop their existing applications to take best advantage of future HPC system architectures. Given limited development and financial resources, it is unlikely that all potential approaches will be evaluated for each application. We are interested in how this decision making can be improved, and this work seeks to directly evaluate three candidate technologies-OpenACC, OpenCL and CUDA-in terms of performance, programmer productivity, and portability using a recently developed Lagrangian-Eulerian explicit hydrodynamics mini-application. We find that OpenACC is an extremely viable programming model for accelerator devices, improving programmer productivity and achieving better performance than OpenCL and CUDA.

I. Introduction

The increasing number of transistors on a chip (as predicted by Moore's law) has provided a continuous, dependable improvement in processor performance for several decades. Traditionally, these additional transistors were used to increase clock speeds, but since the mid-1990s they have been used to increase the number of cores on a single die. Future exascale machines will continue this multicore trend, but limited by power and heat constraints, they will need to be comprised of a much larger number of lower-power, lower-performance cores. Current architectures that offer this style of parallelism include Graphics Processing Units (GPUs), Intel's Xeon Phi, and Accelerated Processing Units (APUs) such as AMD's Fusion. Programming for the large number of lightweight cores offered by these devices means departing from the traditional distributed MPI approach, to a tiered programming model which is designed to harness both coarse and fine grained parallelism.