High-Throughput, Area-Efficient, and Variation-Tolerant 3-D In-Memory Compute System for Deep Convolutional Neural Networks

Untethered computing using deep convolutional neural networks (DCNNs) at the edge of IoT with limited resources requires systems that are exceedingly power and area-efficient. Analog in-memory matrix-matrix multiplications enabled by emerging memories can significantly reduce the energy budget of such systems and result in compact accelerators. In this article, we report a high-throughput RRAM-based DCNN processor that boasts $7.12\mathbf {\times }$ area-efficiency (AE) and $6.52\mathbf {\times }$ power-efficiency (PE) enhancements over state-of-the-art accelerators. We achieve this by coupling a novel in-memory computing methodology with a staggered-3D memristor array. Our variation-tolerant in-memory compute method, which performs operations on signed floating-point numbers within a single array, leverages charge domain operations and conductance discretization to reduce peripheral overheads. Voltage pulses applied at the staggered bottom electrodes of the 3D-array generate a concurrent input shift and parallelize convolution operations to boost throughput. The high density and low footprint of the 3D-array, along with the modified in-memory M2M execution, improve peak AE to 9.1TOPsmm⁻² while the elimination of input regeneration improves PE to 10.6TOPsW⁻¹. This work provides a path towards infallible RRAM-based hardware accelerators that are fast, low power, and low area.

I. Introduction

Deep convolutional neural network (DCNN) processors for edge platforms [1]–[3], such as the IoT require low run-time energy consumption, minimal footprint, short computing latency, and cost-effective solutions. Today, DCNN processors typically use either GPUs [4] or custom-built ASIC [3], [5] for the energy-intensive computing operations. But, the plateauing of transistor count and speed-bottlenecks posed by Von Neumann architecture have made further power and speed improvements in these systems difficult [6]. This stagnation motivates the investigation of more efficient but specialized devices and architectures [6] for faster systems with lower power, area consumption.