Contents I. Introduction
In the last few years, there has been a growing trend to implement DSP functions in Field Programmable Gate Arrays (FPGAs), which offer a balanced solution in comparison with traditional devices. Although ASICs and DSP chips have been the traditional solution for high performance applications, now the technology and the market are imposing new rules [1], [2]. On one hand, high development costs and time-to-market factors associated with ASICs can be prohibitive for certain applications and, on the other hand, programmable DSP processors can be unable to reach a desired performance due to their sequential-execution architecture. In this context, FPGAs offer a very attractive solution that balance high flexibility, time-to-market, cost and performance[1.2]. In the digital video and image processing area, there are many different methods to compress images. Each compression method has different aspects and different characteristics. Among those methods, the compression standard developed by Joint Photographic Expert Group (JPEG) [6] is currently the most widely used in many applications such as web applications. It is because that JPEG compression method can compress large amount of image data into relatively small amount of data size.
