Polynomial Complexity Asynchronous Control Circuit Synthesis of Concurrent Specifications Based on Burst-Mode FSM Decomposition

Asynchronous circuits, despite demonstrated advantages for certain application areas, remain outside of mainstream digital design practices. Existing asynchronous synthesis flows for concurrent specifications either exhibit NP complexity, e.g. incur state space explosion or require the solution of an ILP problem, or cannot guarantee the existence of a solution for the given specification. In this work, we present a P complexity asynchronous synthesis flow, which also guarantees and provides a synthesis solution for any concurrent FCPTnet concurrent specification. This flow has been realised into a novel synthesis tool named Expose. The novelty of our approach and contribution lies in a P complexity methodology for decomposing the FCPTnet specification into a set of interacting, and synthesizable Burst-Mode FSMs. Experimental results, based on scalable asynchronous circuit specifications, and comparison against tools Petrify and Optimist illustrate that our flow enjoys orders of magnitude reduction in execution time compared to the state-space based tool Petrify and significant area savings compared to the direct translation tool Optimist.