Abstract:
With the extensive use of clock-gating in modern microprocessors to reduce the power consumption of the chip, it is imperative to analyze the effect of clock-gating on th...Show MoreMetadata
Abstract:
With the extensive use of clock-gating in modern microprocessors to reduce the power consumption of the chip, it is imperative to analyze the effect of clock-gating on the Power Distribution Network (PDN) and how it affects the voltage drop across the grid. This paper presents a methodology to generate a set of synthetic gating patterns given a power grid, information about how the grid is loaded and regions that belong to different clock-gated domains. Wavelets are used to generate the initial voltage responses as they envelope both the frequency and time domain enabling us to capture frequency information of the PDN to analyze and generate a time-domain signal (voltage drop). The responses generated are then input to a Linear Program (LP) that outputs the worst-case clock-gating patterns and maximum voltage drop at the point of interest. The results show the worst-case gating patterns and the associated voltage drop at a particular point of interest for a set of clock-gated domains. This methodology finds applications in verification of the integrity of the PDN and individual blocks and also, is useful for test pattern generation.
Published in: 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems
Date of Conference: 05-10 January 2013
Date Added to IEEE Xplore: 07 March 2013
ISBN Information: