MOS interface and channel engineering for high-mobility Ge/III-V CMOS

CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of promising devices for high performance and low power advanced LSIs in the future, because of the enhanced carrier transport properties. However, the device/process/integration technologies of Ge/III-V n- and pMOSFETs for satisfying requirements of future node MOSFETs have not been established yet. In this paper, we address gate stack and channel engineering for improving the channel mobility and the MOS interface properties with emphasis on thin EOT and ultrathin body, which are mandatory in the future nodes. As for Ge MOSFETs, GeO
_x
/Ge interfaces formed by plasma post oxidation are shown to realize thin EOT, low D
_it
and high mobility. HfO
₂
/Al
₂
O
₃
/GeO
_x
/Ge gate stacks exhibit record high electron and hole mobility under EOT of 0.76 nm. As for III-V MOSFETs, ultrathin InAs channels with MOS interface buffer layers are shown to provide high electron mobility under InAs thickness of 3 nm. The results of low D
_it
HfO
₂
/Al
₂
O
₃
/InGaAs stacks with CET of 1.08 nm are also presented. A strategy to enhance electron mobility in InGaAs MOSFETs on a basis of physical understanding of the MOS interface properties including high D
_it
inside the conduction band is also addressed.