A highly integrated 65-nm SoC process with enhanced power/performance of digital and analog circuits

65nm Deeply Depleted Channel (DDC
^TM
) transistors have been fabricated with a halo-free, un-doped epitaxial channel and enable reduced threshold voltage (V
T
) variation, lower supply voltage (V
CC
), enhanced body effect and I
EFF
. Digital circuits made using this technology show benefits ranging from 47% power reduction to 38% frequency increase. Analog circuits exhibit 4x greater amplifier gain despite lower V
DD
, and current mirror mismatch (both global and local) shows 40% and 30% reduction for NMOS and PMOS, respectively.