A CMOS track-and-hold circuit with beyond 30 GHz input bandwidth

To realize future ultra high-speed data converters, sampling circuits with very large bandwidth are required. This paper studies the design of ultra high-speed Track-and-Hold (T/H) circuits. A bootstrapping circuit for T/H is presented. The proposed T/H is simulated in 32 nm SOI-CMOS technology. It achieves an input bandwidth higher than 30 GHz and provides an SNDR higher than 43.8 dB (ENOB > 7.0 b) when sampling a 34 GHz input signal at 10 GS/s.