Impact of Gate Resistance on Improving the Dynamic Overcurrent Stress of the Si/SiC Hybrid Switch

A silicon/silicon carbide (Si/SiC) hybrid switch (HyS), comprised of a high-current Si insulated gate bipolar transistor and a low-current SiC metal oxide semiconductor field effect transistors, gains attention because it offers lower
on
-state loss under both light and heavy loads. However, the dynamic overcurrent stress experienced by the HyS under the heavy load has to be coped with to avoid reliability degradation and the maximum current rating limitation. This article comprehensively studies how gate resistances regulate the dynamic behavior of the HyS under the heavy load condition. Experiments and analyses are conducted for both turn-
on
and turn-
off
processes. It is found that the gate resistance is important for not only the d
v
/d
t
control but also the overcurrent suppression. Moreover, the lower switching loss can be achieved by adjusting gate resistances when the HyS operates at a heavy load, compared with the gate timing control. A guideline is developed for the design of the gate resistances. This study offers an insight into the role of gate resistances in switching performances of the HyS and an alternative way of coping with the dynamic overstress stress.