I. Introduction
Phase locked loop (PLL) is a widely used technique for grid synchronization [1]. Since the standard PLL is vulnerable to input unbalance and distortions [2], additional filters are commonly incorporated, such as the moving average filter [3], [4], notch filter [5], delayed signal cancellation operator [6]–[7], dual complex-coefficient filter [8], dual second-order generalized integrator (DSOGI) [9], and others [2]. It is preferable to place the filters before PLL as it does not generate phase delay for the control loop [2]. Besides, parameters of the additional filters are usually frequency adaptive, so as to handle the grid frequency variation in practice. Beneficially, these advanced PLLs could effectively suppress input disturbances at the steady state, even the grid frequency deviates greatly from the nominal value.