An Adaptively Biased Output-Capacitor-Free Low-Dropout Regulator With Supply Ripple Subtraction and Pole-Tracking-Compensation

This article presents an adaptively biased output-capacitor-free low-dropout regulator that achieves high power supply rejection for wearable biomedical system-on-chips (SoCs). Adaptive biasing is implemented to achieve both fast transient responses and high power conversion efficiency, and the common-gate current feedback loop enhances the dc gain of the error amplifier by 10 dB. The proposed supply ripple subtraction reference buffer constitutes a reversed-phase power supply rejection (PSR) path that counteracts the increase in the output voltage due to the in-phase PSR path, and PSR is enhanced significantly in the range of 1 MHz. The proposed pole-tracking-compensation maintains sufficient phase margin over a wide load current range. Designed and fabricated in a 0.18 
$\mu$
m CMOS process, the prototype silicon area is only 0.0113 mm
$^2$
. The total quiescent current is 8.6 
$\mu$
A at no load current, and the maximum current efficiency is 98.8
$\%$
at full load current of 20 mA.