An Optimized Digital Synchronous Rectification Scheme Based on Time-Domain Model of Resonant CLLC Circuit

Uncontrolled rectification on the secondary side of the resonant CLLC circuit causes a large amount of conduction loss. Accurate synchronous rectification (SR) can reduce conduction loss by replacing rectifier diodes with mosfets’ channels exactly. The accuracy of the SR signals depends on the determination of the zero-crossing points of the secondary side resonant current. In this article, an accurate time-domain model is introduced for the resonant CLLC circuit to obtain these zero-crossing points. This modeling method is more accurate than first harmonic approximation and requires less computational effort than extended harmonics approximation. Compared with previous time-domain modeling methods, the proposed time-domain model gives detailed circuit state expressions and covers the entire circuit operating states. Relying on the accurate circuit model, the SR scheme proposed in this article can adaptively generate SR signals in different frequency ranges and has the ability to switch modes smoothly. And this method can be used for the later efficiency optimization of CLLC converters that do not originally have SR function, only through the control program update. Moreover, the robustness of the proposed SR method is analyzed, and the proposed concept is verified through a 3-kW resonant CLLC prototype.