Second-Harmonic Current Reduction for Two-Stage Inverter With Boost-Derived Front-End Converter: Control Schemes and Design Considerations

The instantaneous output power of the two-stage single-phase inverter pulsates at twice the output frequency (2f
_o
), generating notorious second-harmonic current (SHC) in the frontend dc-dc converter and the input dc voltage source. This paper focuses on the SHC reduction for a two-stage single-phase inverter with boost-derived front-end converter. To reduce the SHC, a virtual series impedance, which has high impedance at 2f
_o
while low impedance at other frequencies, is introduced in series with the boost diode or the boost inductor to increase the impedance of the boost-diode branch or boost-inductor branch at 2f
_o
. Meanwhile, for achieving good dynamic performance, a virtual parallel impedance, which exhibits infinite impedance at 2f
_o
while low impedance at other frequencies, is introduced in parallel with the dc-bus capacitor to reduce the output impedance of the boost-derived converter at the frequencies except for 2f
_o
. The virtual series impedance is realized by the feedback of the boost-diode current or the boost-inductor current, while the virtual parallel impedance is implemented by the feedback of the dc-bus voltage. Based on the virtual-impedance approach, a variety of SHC reduction control schemes are derived. A step-by-step closed-loop parameters design approach with considerations of reducing the SHC and improving the dynamic performance is also proposed for the derived SHC reduction control schemes. Finally, a 1-kW prototype is built and tested, and experimental results are presented to verify the effectiveness of the proposed SHC reduction control schemes.