Deep Understanding of Negative Gate Voltage Restriction for SiC mosfet Under Wide Temperature Range

In this letter, the origin and related physical insights of gate reliability issues under various
V
_gs
and high temperatures (up to 300 °C) are revealed in-depth, through splitting MOS gate structure of silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) into N-type JFET and P-type channel region under identical manufacturing processes and thermal budgets of SiC MOSFETs. From 25 to 300 °C, the safety limit of positive
V
_gs
of SiC MOSFETs is mainly dependent on the gate oxide on the JFET surface, whereas that of negative
V
_gs
is dependent on the gate oxide on the channel surface. The gate oxide on the channel surface is weaker than that on the JFET surface in terms of Fowler–Nordheim (F-N) tunneling, resulting in asymmetric safety
V
_gs
of current SiC MOSFET. Moreover, when temperature ranges from 25 to 150 °C, the degradation of gate oxide under −15 V < 
V
_gs
 < 25 V is caused by the hole or electron direct tunneling mechanism. However, when the temperature reaches 300 °C, the degradation of gate oxide under −5 V < 
V
_gs
 < 10 V is caused by the hole or electron hopping conduction mechanism. Furthermore, the reliability of gate oxide is evaluated by the time-dependent dielectric breakdown measurement. The charge-to-breakdown (
Q
_BD
) of gate oxide is severely degraded at 300 °C mainly due to the barrier height (
${\it{ \Phi}}_{\rm B}$
) degradation. These efforts can provide accurate weakness points of gate oxide under higher
V
_gs
bias (particular for negative bias) and higher temperature (300 °C) for SiC MOSFETs, further helping use and design rugged converters with the fast-speed operation of SiC MOSFETs.