Modeling Avalanche Induced Degradation for 4H-SiC Power MOSFETs

In this letter, a model that predicates the degradation of 4H-SiC power metal-oxide-semiconductor field-effect transistors under repetitive avalanche stress is proposed. Since positive charges are injected into the gate oxide interface of the JFET region, the gate-drain capacitance (C
_gd
) is chosen as the targeted parameter to quantify the avalanche induced degradation. The relationship between the increment of the C
_gd
and the injected charge density is calculated and validated to demonstrate the rationale of the model. It is found that the increment of C
_gd
has a linear relationship with the logarithm of the total avalanche energy (E
_AV
) dissipated on the device. Excellent agreement is also achieved between the simulated degraded data and the measured one, further proving the accuracy of the proposed degradation model.