An Efficient Implementation of Generalized Delayed Signal Cancellation PLL

The phase, frequency, and amplitude of the fundamental-frequency positive-sequence component of the grid voltage are crucial information in control of most grid-connected power electronic based equipment. Often, a standard phase-locked loop (PLL) with a prefiltering stage is employed for the extraction of this information. Inspired by the concept of delayed signal cancellation (DSC), the generalized DSC (GDSC) operator has recently been introduced as an interesting option for the PLL prefiltering stage. In its typical structure, the GDSC operator extracts the grid fundamental component and feeds it to a conventional synchronous reference frame PLL (SRF-PLL). The frequency estimated by the SRF-PLL is then fed back to the GDSC operator to make it frequency adaptive. This structure, however, suffers from two main drawbacks: 1) the system is highly nonlinear, and therefore, it is difficult to ensure its stability under all circumstances; and 2) adapting the GDSC to grid frequency variations increases the implementation complexity and computational effort, particularly when the interpolation techniques are used for this purpose. To avoid these problems while maintaining high accuracy in the extraction of grid voltage quantities, an efficient and low-cost implementation of the GDSC-PLL is suggested in this paper. The proposed structure, which is called the enhanced GDSC-PLL (EGDSC-PLL), uses a nonadaptive GDSC operator as its prefiltering stage and corrects the phase-shift and amplitude scaling caused by this operator by using two units, called the phase-error compensator and amplitude-error compensator. The effectiveness of the EGDSC-PLL is confirmed through simulation and experimental results.