Dynamic Partial Reconfiguration of Concurrent Control Systems Specified by Petri Nets and Implemented in Xilinx FPGA Devices

This paper proposes a novel design concept of concurrent control systems specified by interpreted Petri nets and implemented in Xilinx FPGA devices. The technique is oriented on further dynamic partial reconfiguration of the system. An adequate splitting algorithm of the system into the dynamic (reconfigurable) and static (non-reconfigurable) partitions is proposed. The main advantage of the presented idea is the possibility of the dynamic reconfiguration of the already implemented system. It means that the functionality of the selected component (module) of the controller can be changed, while the rest of the system is still running. The presented technique is illustrated by a real-life case-study example, and it has been verified experimentally with the application of Xilinx FPGA device.