Zero-Sequence Circulating Current Analysis and Suppression for Multimodular Interleaved Parallel Inverters

Modular interleaved parallel inverters with shared dc and ac bus will introduce the zero-sequence circulating current (ZSCC) between the paralleled modules. Larger ZSCC may increase the current stress of power switches and reduce system efficiency. In this article, the ZSCC equivalent circuit model with multimodular interleaved parallel inverters is established. The influences of different factors such as carrier phase shifting, unequal current references, dead time, and unequal inductors on the high-frequency ZSCC (HF-ZSCC) and low-frequency ZSCC (LF-ZSCC) are analyzed in the frequency domain. An interleaved zero vector modulation method is proposed together with a plug-in repetitive controller to suppress HF-ZSCC and LF-ZSCC simultaneously. With the proposed method, parallel modules can be implemented in a self-governing manner, which presents high reliability and scalability. The effectiveness of the proposed scheme is verified by the experimental results.