Understanding the Degradation of 1.2-kV Planar-Gate SiC MOSFETs Under Repetitive Over-Load Current Stress

Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) has superior performances in terms of high switching frequency and low power loss, but its widespread applications in markets have been partly hindered by its ruggedness and reliability. Overcurrent operation is a common phenomenon which causes overheat of power devices and further leads to degradation or even device failures in power electronic systems. However, in- depth degradation mechanism and limiting factors of repetitive overcurrent capability have not been comprehensively studied yet. In this article, we investigated the conduction and the switching overcurrent stress separately to figure out the roles of each operation processes in the degradation of 1.2-kV SiC planar-gate MOSFETs for the first time. It is observed that the conduction overcurrent stress causes a positive shift of threshold voltage, while the switching overcurrent stress leads to a negative shift of threshold voltage as well as larger gate leakage current. Electrons captured at the SiC/SiO2 interface may be the reason for the positive shift of threshold voltage, while the negative shift of threshold voltage may be due to the injection and accumulation of the holes into the gate oxide at JFET and near-channel region. Both experimental results and simulation analysis show that the switching overcurrent stress plays a major role in the degradation of 1.2-kV SiC planar-gate MOSFETs under repetitive overcurrent stress. In addition, the influence of major limiting factors, including overcurrent level, overcurrent duration, and drain–source voltage, is also investigated to evaluate the reliability of SiC planar-gate MOSFETs under different overcurrent conditions, which will provide a useful guidance for dedicated design and utilization of SiC MOSFETs.