Frequency Doubler Gate Drive Circuit Suitable for High-Frequency Applications

In megahertz (MHz) power converters, the gate drive loss becomes one of the main issues that should be addressed. In the relevant literature, several gate drive circuits had been proposed to reduce the gate drive losses. A literature survey is provided in the introduction section to summarize the merits and demerits of each circuit. These studies proposed innovative methods to reduce gate drive loss. Nonetheless, they did not propose any solution to reduce the loss of the buffer stage inside the drive IC. In this article, we present a frequency doubler gate drive circuit. The proposed gate drive circuit can double the frequency of the input PWM signal at the driver output stage, using the second harmonic of the input signal. Therefore, the loss of the buffer stage inside the drive IC can be significantly reduced, compared with the hard-switching, the inductive resonant, and multiresonant gate drive circuits. This article focuses on designing, simulating, and experimentally validating the frequency doubler gate drive circuit with a 6.78-MHz input frequency and 13.56-MHz driving frequency. The concept of a frequency tripler gate drive circuit is also introduced and discussed. For instance, the frequency tripler gate drive circuit can triple the frequency of the input PWM signal at the driver output stage using the third harmonic; in this scenario, a 20.34-MHz driving frequency can be obtained. The proposed frequency doubler gate drive circuit is experimentally tested in a 13.56-MHz class E inverter.