Investigation of Damping Effect of PLL on Low-Frequency Harmonic Stability of Grid-Tied Inverter With αβ and dq Current Control Schemes

The choice of phase-locked loop (PLL) bandwidth in three-phase grid-tied inverters (GTIs) is always a tradeoff between robust performance under distorted grid conditions and fast detection of grid voltage phase angle during the low-voltage ride through. Besides, even though both the GTI with decoupled
dq
-frame (CC1) and
${\alpha \beta }$
-frame (CC2) current control schemes employ PLL for grid synchronization, and damping effect of PLL, which is a function of its control bandwidth, is not identical. As a consequence, the output impedance of GTI with CC1 and CC2 has diverse interaction scenarios with the weak grid impedance. Therefore, this work investigates the impact of PLL bandwidth on the output impedance of GTI in the two different current control schemes using impedance models in a common frame of reference (
dq
-frame here). Negative damping region exhibited by
${q}$
-axis impedances are identified. It is found that CC2 has a less significant negative damping region, while that of CC1 widens with the increase in PLL bandwidth. Furthermore, the side effects of dissimilar damping regions on inverter-grid system stability are demonstrated through the impedance interaction analysis. The output impedance shaping caused by voltage feedforward and outer power control loops on CC1 and CC2 is also investigated. Finally, a compensator is designed to overcome the phase lag introduced by PLL and voltage feedforward loop. The above findings are validated through MATLAB/Simulink simulations and experiments.