Switching Performance Analysis of Vertical GaN FinFETs: Impact of Interfin Designs

This article studies the switching performance of vertical GaN power FinFETs and proposes new interfin designs to improve it. The interfin region has been found to be an important limiting factor for FinFET switching performance. The time taken to (dis)charge the dielectric parasitic capacitances and drift layer in the interfin regions severely limits the device turn-(on)off speed. Three new interfin designs are proposed, based on reduced fin-to-fin spacing, oxide full-filling (FF), and split-gate (SG) structures. The 1.2-kV, 80-mΩ vertical GaN FinFETs with these designs were evaluated by a well-calibrated device-circuit mixed-mode technology computer-aided design (TCAD) simulation. Both the reduced-fin-spacing structure and the oxide FF reduce the dielectric parasitic capacitances, but only lead to small reduction (less than 10%) in switching losses. Much better improvement is obtained with the SG structure, which removes the gate metal in the interfin region and exposes the drift layer to the field lines from the source metal. During the turn-(on)off of the transistor with a SG structure, the drift layer underneath the interfin gap region is (dis)charged by a combination of the drain-to-source and gate currents, leading to shorter switching times and lower switching losses. By utilizing the SG structure, simulations predict a 58% improvement in the switching figure-of-merit and 38% lower switching losses in 1.2-kV vertical gallium nitride (GaN) power FinFETs. These results provide key understanding and design guidelines for power FinFETs. Finally, an 800-V buck converter using a 1.2-kV GaN FinFET half-bridge module is simulated, showing excellent efficiency when operating at a multi-MHz frequency and revealing the requirement for device thermal management. This highlights the great potential of vertical GaN power FinFETs for future high-frequency medium-voltage power applications.