Adaptive Dead-Time Compensation for High-Frequency Three-Level Sparse NPC Inverter

A promising three-level (3L) topology for ultrahigh-speed (UHS) motor applications is a sparse neural point clamped (SNPC) inverter that can generate 3L voltage output and is the cheapest among other 3L counterparts. Using all SIC switches can increase the switching frequency and considerably improve the performance of the UHS drive system. However, increasing the switching frequency results in a significant dead-time effect. Therefore, the quality of the output phase current reduces considerably. Compared with other conventional 3L and two-level (2L) topologies, the SNPC topology has a distinct dead-time voltage error generation principle. Therefore, dead-time compensation methods cannot be directly applied. In this study, first, the dead-time voltage error generation principle for SNPC topology was analyzed. Next, the obtained voltage error expressions were used to perform the Fourier analysis. The derived dead-time voltage error equations in the frequency domain are compared with other conventional 2L and 3L topologies. Finally, a novel adaptive dead-time compensation method was proposed based on the results obtained from the Fourier analysis. An experimental setup based on the high-frequency SIC-SNPC inverter and UHS motor was developed to verify the feasibility of the proposed compensation method.