Reduced-Order Generalized Integrator-Based Phase-Locked Loop: Performance Improvement for Grid Synchronization of Single-Phase Inverters

Generalized integrator-based orthogonal signal generator phase-locked loops (GI-OSG PLLs) are very popular in single-phase grid synchronization. Generally speaking, the OSG of this PLL is realized from a second-order integrator perspective. As a result, the OSG implementation impacts the PLL dynamics. Improving the PLL performance by employing a reduced-order OSG implementation is the main motivation for this paper. Therefore, a reduced order-OSG PLL is proposed. In the proposed PLL, a single state and two output equations are employed to obtain a pair of orthogonal signals. This results in the loss of orthogonality between the OSG outputs and the single-phase supply voltage. Also, harmonic filtering capability provided by SOGI-OSG becomes non-existent. These issues are resolved by incorporating steady-state phase angle-offset error compensation at the PLL output and a moving average filter (MAF) within the PLL loop. To counteract the influence of MAF on the PLL’s stability and dynamics performance, a phase-lead compensator is designed. Through experimental studies, it is shown that the proposed reduced order-OSG PLL offers excellent dynamic performance. Also, the proposed PLL achieves minimal fluctuation of PV power when employed for grid synchronization of a PV system.