An Improved PLL Topology to Mitigate Commutation Failures for LCC-HVDC Systems Under Asymmetrical Faults

The Phase-Locked Loop (PLL) synchronizes the firing signals of the thyristor valves with the inverter bus voltages so its output is inevitably affected by the inverter bus voltage inputs under asymmetrical faults. This paper analyzes the impacts of the phase angle shifts of the commutation voltages and the Point on Wave (POW) of AC faults on the PLL output as well as the commutation process. It is found that phase angle shifts of commutation voltages and POW can either advance or delay the PLL output, leading to either a beneficial or detrimental impact on commutations. This means that simple reductions of inverter firing angle under all fault cases are not necessary and may cause undesirable increase of reactive power consumptions and voltage drops when the phase angle shifts are beneficial for commutations. Therefore, to accurately eliminate the detrimental impact, an improved Fault Inversion Module (FIM) based PLL topology is proposed. It eliminates the phase angle delay of the PLL output under asymmetrical faults, and thus suppresses commutation failures (CFs). The effectiveness of the proposed FIM-PLL in mitigating CFs is demonstrated by simulations of the CIGRE LCC-HVDC Benchmark on RTDS and comparisons with the CF Prevention Control Module (CFPREV).