Synaptic Weight Evolution and Charge Trapping Mechanisms in a Synaptic Pass-Transistor Operation With a Direct Potential Output

We present an intensive study on the weight modulation and charge trapping mechanisms of the synaptic transistor based on a pass-transistor concept for the direct voltage output. In this article, the pass-transistor concept for a metal–oxide–semiconductor field-effect transistor is employed to a synaptic transistor with a charge trapping layer, which is named a synaptic pass transistor (SPT). Based on this SPT concept, the voltage signal would be provided at the output terminal directly without requiring a complicated circuitry, whereas the conventional synaptic transistor with the current output needs a conversion circuit. For the SPT, the definition of the synaptic weight as a transfer efficiency and operation principles of the SPT with charge-trapping mechanisms is analyzed theoretically. The respective semiconductor device simulation results, such as synaptic output and weight modulations as a function of time for a synaptic depression and facilitation, are presented with detailed analysis. Also, it is shown that an SPT array configuration can perform a synaptic scaling by itself, i.e., a self-normalization of the weight, which is confirmed with the simulation results of learning a simple classification example. Moreover, to verify the potential usage of the SPT array as an analog artificial intelligence accelerator, a classification task for a standard data set, e.g., Modified National Institute of Standards and Technology database (MNIST), is also tested by monitoring the accuracy. Finally, it is found that SPTs proposed here can exhibit low power consumption at a device level as well as sufficient accuracy at the array level while more closely mimicking the biological synapse.