Challenges and solutions for core power distribution network designs

Core power decoupling for modern processors or SOCs is a challenging task due to large power consumption. A conventional target impedance method can no longer be used in modern high-performance core PDN design. In this paper, we first demonstrate major issues and challenges in existing PDN modeling methodologies. Then, we present a comprehensive list of PDN improvements which significantly eliminates pessimism built in existing methods. In particular, we propose an improve VRM model to reduce the PCB bulk cap requirements, an accurate PCB decoupling frequency range to reduce the PCB SMC cap, a modified target impedance concept to account for realistic ramp time for large load change, and a novel timingbased PDN design methodology to further reduce any pessimism in traditional noise based PDN design methodology.