A New Type-2 PLL Based on Unit Delay Phase Angle Error Compensation During the Frequency Ramp

This letter introduces a unit delay compensation scheme for Type-2 phase locked loop (Type-2 PLL) to eliminate the steady state phase angle error during the frequency ramp. The proposed PLL (ZPLL) uses an adaptive delayed signal cancellation (DSC) filter, along with a compensation scheme, to ensure effective operation under unbalanced grid. The proposed compensation scheme acts as an open-loop compensator, hence, ZPLL functions as Type-3 PLL with Type-2 dynamics features while preserving its second order characteristics. The proposed scheme is mathematically and experimentally validated under different scenarios of grid disturbances. The obtained results demonstrate the capability of the proposed compensation scheme to obtain a zero steady state phase angle error during the frequency ramp while employing symmetrical and asymmetrical voltage dip.