Structural Integrity of 3-D Metal–Insulator–Metal Capacitor Embedded in Fully Filled Cu Through-Silicon via

A novel way to implement integrated metal–insulator–metal (MIM) capacitor with ultrahigh capacitance density of up to 5.621.8 nF/mm
²
has been proposed earlier. This technology embeds 3-D MIM capacitor into the existing trench of through-silicon via (TSV) prior to Cu filling to achieve >90% planar surface area reduction. However, the previous study was on the early-stage test vehicles without Cu filling. In this work, complete test vehicles with fully filled Cu TSVs have been successfully fabricated whose trench diameters are 0 (D00), 10 (D10), 20 (D20), and 30
$\mu \text{m}$
(D30), respectively. First, the design layout and the process flow are disclosed in detail. Then under scanning electron microscope (SEM) and transmission electron microscope (TEM), it is found that the peak of the Si scallop on the sidewall is deformed for the D30 test vehicle. For the first time, the damage is found in Si substrate, instead of TSV SiO
₂
liner, due to the thermomechanical stress between the TSV Cu core and the surrounding structures. In addition, the Al
₂
O
₃
dielectric layer is also impaired at the damaged Si peaks. Finally, the leakage current density is measured and normalized at a bias of 1.5 V:
$4 \times 10^{-9}$
A/cm
²
for D00,
$4.1\times 10^{-8}$
A/cm
²
for D10, 1.1
$\times 10^{-6}$
A/cm
²
for D20, and
$7.4\times 10^{-1}$
A/cm
²
for D30, respectively. Therefore, the structural integrity of the D10 and D20 test vehicles with fully filled Cu TSVs is preserved, but the D30 test vehicle is not intact due to higher stress. The capacitance density of 6.547.1 and 7.091.7 nF/mm
²
is recorded for the D10 and D20 test vehicles, respectively.