IC Debug and Fault Isolation for an Age of IoE and High Data Rates—A Vision

The electronics industry faces an explosion of data collection, exchange and storage for the Internet of Everything, cloud computing, and many more applications. A dramatic performance gain of circuits and systems will be required, including a drastic increase of operating frequency, combined with very low power and low latency—all this at no cost increase. Although the International Technology Roadmap for Semiconductors, representing the progress of Moore’s law, edited their final report in 2016, it can easily be predicted that electronic systems and packages will undergo enormous miniaturization and new interconnect concepts involving new materials and solutions, called “heterogeneous integration.” First silicon debug and diagnosis and failure analysis (FA) rely on internal signal tracking using contactless fault isolation (CFI). CFI is performed from the chip backside utilizing near-infrared optical probe that interacts with the logical signal. This paper assesses CFI readiness for the expected evolution on chip level and system/package level. Challenges and new opportunities will be discussed that CFI encounters with 3-D integration and photonic interconnects. Together with innovations in test, reliability, and security, a vision and several options are presented. They indicate how challenges to CFI may be mastered by new concepts of debug and FA, when they are part of the design concept of the electronic systems from early on.