A Dual-Mode Wideband +17.7-dBm 60-GHz Power Amplifier in 65-nm CMOS

This paper presents a 60-GHz power amplifier (PA) utilizing a novel technique to achieve high efficiency at high output power levels. The proposed topology provides the capability of dual-mode operation. The output power of a conventional class-A power amplifier will be combined with the power provided by an amplifier operating at a different class to achieve higher efficiency at higher output levels. An enhanced cascode stage is designed to boost the power gain provided by driver stages coupled to the power stage with transformer-coupled impedance matching networks. Fabricated in 65-nm CMOS process, the measured gain of the 0.32-mm
²
power amplifier is 17.7 dB at 60 GHz with a wide 3-dB bandwidth of 12 GHz while consuming 378 mW from a 1.2-V supply. A maximum saturated output power of 16.8 dBm is measured with the 14.5% peak power added efficiency (PAE) at 60 GHz. The proposed PA achieved a measured maximum PAE of 17.2% at 18.1-dBm-saturated power operating in high-power mode by applying 1.4-V supply.