Probe-Pad Placement for Prebond Test of 3-D ICs

3-D integrated circuits (3-D ICs) are emerging as a promising alternative to continue the scaling trajectory. They need to be tested before bonding (prebond) to ensure high stack yields. Several techniques exist for prebond test of 3-D ICs, and all of them require large probe pads for power delivery. We present the first probe-pad-aware 3-D IC placement framework, and this provides up to a 2% reduction in the wirelength and significant improvement with regard to testability metrics. In addition, we study several probe-pad configurations, and present a configuration that reduces the probe-pad count by 50% compared with adding a probe pad at every power/ground through-silicon-via location, while still being well within IR-drop constraints.