I. Introduction
The limited performance improvement of transistors in ultradeep-micrometer technologies is making it more difficult to achieve computing performance increases from scaling alone [1]. Transistors are still getting smaller, but their performance is not increasing at a pace consistent with Moore’s law. Furthermore, migration to advanced process nodes is facing tremendous cost increases in lithography and patterning integration [2], slow rampup in manufacturing yield, and large variations in the electrical characteristics of MOSFETs. This situation is further aggravated by the growing complexity of interconnects. The average length of global wires is determined by chip size and tends to remain fixed as technology scales, but the delay of a unit length of wire is increasing [3]. Furthermore, the slowdown in supply voltage scaling makes it more difficult to reduce power consumption. 3-D integrated circuits (3-D ICs) address some of these challenges by stacking different ICs vertically [4], [5]. Circuits in different tiers of a 3-D IC can communicate with each other through different types of through-silicon vias (TSVs), which can largely reduce the total wire length and routing congestion compared with a conventional 2-D implementation. This results in reduced interconnect delay and power consumption. A 3-D IC also enables integration of disparate technologies [such as technologies supporting radio frequency (RF) and high-performance logic devices] in a monolithic 3-D die. This type of heterogeneous integration is a powerful means of reducing delay and power consumption [6–8]. Furthermore, even within one technology, different generations (for example, 45- and 32-nm logic CMOS) can be stacked to realize the cost benefit from the better yield of the mature node [9].