High-Yield Fabrication Process for 3D-Stacked Ultrathin Chip Packages Using Photo-Definable Polyimide and Symmetry in Packages

Getting output of multiple chips within the volume of a single chip is the driving force behind development of this novel 3D integration technology, which has a broad range of industrial and medical electronic applications. This goal is achieved in a two-step approach. Initially, thinned dies are embedded in a polyimide interposer with a fine-pitch metal fanout, resulting in ultrathin chip packages (UTCPs). Next these UTCPs are stacked by lamination. Step height at the chip edge of these UTCPs is the major reason of die cracking during the lamination. This paper contains an approach to solve this issue by the introduction of an additional layer of interposer, which makes it flat at the chip edge and thus the whole package is named as flat-UTCP. In addition to that, randomness in nonfunctional package positions per panel reduces the overall yield of the whole process up to a certain extent. A detailed analysis on these two issues to improve the process yield is presented in this paper. 3D-stacked memory module composed of four electrically erasable programmable read-only memory dies was processed and tested to demonstrate this new concept for enhancing the fabrication yield.

I. Introduction

An effective approach in miniaturizing the size of electronic packages is to make use of the third dimension by creating vertical interconnections. A tremendous demand for this packaging concept is found in the future generation portable, cheap, and smart electronics devices. Hence, the large efforts in research are made toward chip embedding and chip stacking using through silicon via technologies. In the framework of the european project TIPS, the process for 3D-stacking of ultrathin chip packages (UTCPs) was developed to provide another way for fabricating devices with a minimal package volume. An overview of this technology resulting in the fabrication of a 300 thick stack of four EEPROM memory dies was previously reported in [1] and [9]. This process is based on the first generation of UTCPs, which consists of a chip embedding technology within two spin-on polyimide layers [2]. The polyimide membrane of these packages has a total thickness of 40 , however, where the thinned die is embedded a topographical difference of 15–25 exists. Furthermore, the presence of the silicon die results in more and less flexible areas in the interposer. The combination of both mechanical characteristics resulted in an increased risk of die cracking during the lamination process. This effect has been reported in [9]. To control this risk of cracking, the topography can be reduced, thus creating a flat-UTCP (Fig. 1). Fig. 1.

Schematic overview of stacking of flat-UTCP approach.