I. Introduction
Wafer-level packaging (WLP) of CMOS imager sensors and microelectromechanical system (MEMS) devices has gained much attention recently, along with the 3-D stacking of die with through-silicon-vias (TSVs) interconnects [1], [2]. For the 3-D integration of MEMS devices, the packaging is required to have a small footprint. In addition, packaging for MEMS devices requires the parasitic effects of packaging to be minimal on the MEMS performance, especially on the radio frequency (RF) characteristics [3]. Hence, WLP with low insertion loss is a promising solution for the MEMS device packaging and 3-D integration.