Liquid Metal Interconnects for High Pin Count Scaling and Socketing Applications

The omnipresent demand for more compute power along with an increase in memory and high-speed signaling input–output (HSIO) bandwidth are key drivers behind the exponential growth in board/second level interconnect (SLI) pin count, processor package size and thermomechanical enabling complexity. There is also an increasing desire for low-cost separable interconnect solutions with a “late attach” option for better inventory control and allowing replacement of the processor packages to enable in-field upgrade/repair and meet reliability, availability, and serviceability (RAS) requirements. Incumbent interconnect technologies like socket-type land grid array (LGA) or permanently soldered down ball grid array (BGA) come with inherent limitations that are not scalable and do not meet future yield, performance, total cost of ownership (TCO), and system-on-chip (SoC) density demands. In this article, we discuss a novel approach to overcome these limitations. The proposed solution uses gallium-based liquid metal (LM) interconnects that do not require sustained mechanical load to achieve a stable electrical connection, unlike LGA, and, hence, decouple pin count scaling from mechanical loading complexity. In addition, LM interconnects offer the benefit of reduced lower-level contact resistance (LLCR) with the elimination of constriction resistance between the conductors as compared to LGA. In this article, we discuss the feasibility of LM interconnects for board/SLI applications, benefits of the technology to meet future scaling needs.