A Cost-Effective Solution for Testing High-Performance Integrated Circuits

Testing of high-speed integrated circuits that enable 100-Gb Ethernet is a complex and expensive proposition. It becomes increasingly difficult to carry out measurements with probes if the test chip's pad count is very high. A full-fledged packaging solution to test a chip requires a lot of resources and incurs a considerable cost. Other approaches, such as using flip-chip-on-board, prove to be expensive as well. On-board electrical interconnects, if appropriately designed, can be used with wire-bonded dies to perform high-speed measurements using ordinary methods. This article discusses the design and development of a platform to test a high-speed equalizer chip designed for the 100-Gb/s dual polarization-quadrature phase shift keying-based optical links. It also shows how careful optimization of the test platform addressing the aspects of signal delivery from connectors to chip pads through broadband transmission lines and bond-wire transitions and thermal management facilitates the use of low-cost methods to test high-performance chips. Detailed descriptions of the test platform and its validation using S-parameter measurements and the experimental results with an optical system are also presented.