I. Introduction
As hardware technology continues to advance at a pace exceeding Moore’s law predictions, the optimization of integrated circuit (IC) design has become increasingly sophisticated and challenging. This complexity is driven by the surging demand for high-bandwidth, high-frequency systems due to the ever-growing volume of processed data. These advanced systems are designed using 2.5-D integration technology, which allows for the integration of heterogeneous chiplets, such as GPU and high-bandwidth memory. In 2.5-D integration, numerous I/Os from multiple heterogeneous chips are interconnected through an interposer, enabling scalability and cost-effectiveness in manufacturing. Considering interposer interconnection, the fundamental goal is to minimize wirelength as it substantially impacts the energy consumption and signal latency of 2.5-D ICs [1].