Understanding the Interplay Between CdSe Thickness and Cu Doping Temperature in CdSe/CdTe Devices

CdSe thickness and Cu doping play significant roles in achieving high efficiency in CdTe solar cells. Using an evaporated CdSe/CdTe device stack to avoid vacuum breaks between deposition of layers, we investigated the role of the CdSe thickness on the device performance. When the CdSe thickness was greater than a critical value the device performance suffered primarily due to a reduction in the short-circuit current density (J
_SC
). The critical thickness of CdSe was determined to be 120 nm. However, in some cases the CdSe thicknesses could be increased to larger values by increasing the Cu doping process temperature. The higher temperature process leads to an increase in J
_SC
and an overall improvement in device efficiency. Specifically, for a device with ∼270 nm of CdSe, the J
_SC
increased from 7.9 mAcm
⁻²
with CuCl
₂
processing temperature of 200°C to ∼29 mAcm
⁻²
when the processing temperature was increased to 250°C.