3D AND-Type Ferroelectric Transistors for Compute-in-Memory and the Variability Analysis

Three-dimensional AND-type architecture (3D AND) based on ferroelectric field-effect transistors (FeFETs) is proposed for the vector-matrix multiplication (VMM) of compute-in-memory paradigm. By leveraging a vertical string as one synaptic element, multibit weight with controllable linearity is realized due to parallel connection of cells in a string. Multibit input is also feasible with appropriate word line (WL) biasing. To guarantee the deep neural network performance, the device-level conductance distribution should be tightened. The phase variation of ferroelectric layer is regarded as a primary variation source, and its impact on the inference accuracy is examined.