New Strained Silicon-On-Insulator Lateral MOSFET With Ultralow ON-Resistance by Si1-xGex P-Top Layer and Trench Gate

A novel ultralow on-resistance strained silicon-on-insulator (SOI) lateral double-diffused MOSFET with silicon-germanium (Si
_1-x
Ge
_x
) P-top layer and trench gate (P
_SiGe
-TG LDMOS) is proposed in this letter. The Si
_1-x
Ge
_x
P-top layer (P
_SiGe
) as a stressor introduces the beneficial stress in the drift and channel regions to enhance the electron mobility. Besides, in the off state, both P-top layer and trench gate (TG) jointly assist in depleting the N-drift region, which leads to an allowable highly-doped N-drift region. As a consequence, P
_SiGe
-TG LDMOS realizes an ultralow specific on-resistance ( R
_on,sp
) resulting from the highly-doped N-drift region. Furthermore, the enhanced electric field in the trench oxide leads to an increase in breakdown voltage (BV). The simulation results show that, compared with the trench-gate SOI LDMOS (TG LDMOS) and the trench-gate SOI LDMOS with Si-based P-top layer (P
_Si
-TG LDMOS), the introduction of P
_SiGe
layer leads to 42% and 26% reduction in R
_on,sp
, respectively. The figure-of-merit (FOM) of P
_SiGe
-TG LDMOS increases from 8.1 MW/cm
²
of TG LDMOS and 9.4 MW/cm
²
of P
_Si
-TG LDMOS to 12 MW/cm
²
, which realizes a superior performance.